1. Field of the Invention
The present invention relates in general to a semiconductor process. In particular, the present invention relates to a method of using an image resist acting as a sacrificial layer for an inter-level dielectrics (ILD), and forming a contact opening in inter-level dielectrics (ILD) without etching.
2. Description of the Related Art
As ICs become more compact, semiconductor designs have reduced device dimensions. For example, the 64 M DRAM process has shifted from 0.35 xcexcm to 0.3 xcexcm or less, and the 128 M and 256 M DRAM process to less than 0.2 xcexcm.
In the contact process of the array area of a memory unit, the transistor arranges with high density, so a self-aligned contact (SAC) process is typically employed to enhance precision and accuracy. First, the (boro-phosphosilicate glass (BPSG), tetracthoxysilane (TEOS) stacked layers, and the silicon oxide materials, are used to as an inter-level dielectrics (ILD, the insulator layer) covering the transistors, then a SAC bit line contact (CB holes) is formed in the insulator layer using an etching process, the polysilicon material is then filled into the bit line contact to serve as a bit line contact plug. Subsequently, a contact holes process is carried out in the array area which a gate electrode contact (CG holes) and a junction contact (CS contact) are formed in the above insulator layer. Next, the bit line conductive wire MO is etched to define the contact location of the bit line contact plug.
When the ILD is etched, the BPSG/TEOS insulator layer is etched through to expose junction area, exposing the silicon substrate to potential damaged, which results in a serious sub-threshold voltage (sub-Vt) problem, impacting the memory ability of the capacitor in the array area. Additionally, when the ILD is etched, the spacers on the sidewall of the gate electrodes (word line) are easily damaged, resulting in short circuits between word line and bit line. Moreover, when a semiconductor design has reduced device dimensions, the width between the gate electrodes is reduced, impeding the etching process, and resulting in open circuits.
FIGS. 1xcx9c2 show the conventional self-aligned contact fabrication resulting in bit line open circuits or word line/bit line short circuits.
Subsequently, in FIG. 1, the pad silicon nitride layer 28, the BPSG layer 30, and the TEOS 32 stacked insulator layer are formed on the silicon substrate 10 with the transistor structure, wherein the pad silicon nitride layer 28 is employed to prevent the B+/P+ of the BPSG layer 30 diffusing to the silicon substrate 10 when a thermal process is performed, impacting the device characteristics. The transistor includes source 12, drain 14 and gate structure 20, the gate structure 20 includes gate oxide layer 21, polysilicon layer 22, tungsten silicon layer 23, silicon nitride layer 24 and silicon nitride spacer 25, on the sidewall of the gate structure 20, wherein the gate electrode consists of the polysilicon layer 22 and the tungsten silicon layer 23. Next, a resist layer 40 is formed on the TEOS layer 32, with a contact opening pattern, then, using the resist layer 40 as a mask, the BPSG layer 30/TEOS layer 32 is etched to form a contact opening 34. Since the contact opening 34 widths of the exposed drain area 14 between the gate electrodes are less than 0.030 xcexcm when the line width is minimized to about 0.09 xcexcm, and, the BPSG layer 30/TEOS layer 32 stacked insulator layer is very thick, the ILD is more difficult to etch when closer to drain area 14, and once the etching reaction is complete, incomplete or unetched insulator residue 30xe2x80x2 remains in the bottom of the contact opening 34, preventing exposure of the drain area 14. When the insulator residue 30xe2x80x2 is not a conductor, the subsequently filled conductive material cannot be electrically connected, resulting in the described bit line contact open circuits.
In order to prevent open circuits, in FIG. 2, a conventional method uses overetching to etch the insulator residue 30xe2x80x2 and the pad silicon nitride layer 28, however, the etching selectivity of the silicon oxide material to the silicon nitride spacer is only around 10xcx9c15, and the silicon nitride layer 24 and the silicon nitride spacer 25 are easily removed, exposing the tungsten silicon 23 and polysilicon 22 of the gate electrodes, resulting in word-line/bit-line short circuits
Additionally, BPSG possesses excellent gap filling characteristics even if the line width is reduced to 0.09 or 0.07 xcexcm; however, the width between the gate electrodes is minimized when the line width dimension is reduced, such that the gap between the gate electrodes is difficult to fill even with BPSG material, resulting in voids and leading to short circuits between the adjacent contacts of the individual bit lines. Different from FIGS. 1 and 2, FIG. 3 shows that the two drains 14 are a portion of the transistor of the individual bit line. After etching the BPSG 30 and TEOS 32 stacked insulator layer to form a contact opening 34 using resist layer 40 as a mask, the resist layer 40 is then removed. Next, the contact opening 34 is filled with conductive material to form bit line contact plug 38. Once the contact opening 34 forms void 36, the conductive material is also filled into the void 36, resulting in short circuits between contact plugs 38 of adjacent bit lines.
Accordingly, an object of the invention is to provide a method of forming a contact opening, and preventing the silicon substrate from damage during, for example, bit line contact etching.
Another object of the invention is to provide a method of forming a contact opening, and preventing the contact from open circuits due to narrow width between the gate electrodes.
Another object of the invention is to provide a method of forming a contact opening, and preventing word line/bit line from short circuits.
Another object of the invention is to provide a bit line contact process, and preventing contact plugs from short circuits due to the voids in the inter layer dielectric (ILD).
In order to achieve the above objects, the invention provides a method of forming a contact opening, comprising providing a substrate with transistors protected by a silicon-containing insulator layer, then, covering a non-silicon-containing resist layer on the substrate, with a level surface, next, covering a silicon-containing thin resist layer on the non-silicon-containing resist layer to form a stacked resist layer, with a level surface, patterning the stacked resist layer to form a resist stacked layer with a contact plug pattern overlying the doping areas, next, forming an insulator layer on the resist unmasked area using a selective deposition process, removing the stacked resist layer to expose the doping area, and forming a contact opening.